After the semiconductor integrated circuit technology reaches the 90 nm node and beyond, it is becoming more and more challenging to maintain or even improve performances of transistor devices. At present, the strained silicon technology has become a fundamental one, which improves performances of MOSFET devices by suppressing short channel effects and enhancing the mobility of carriers. For a PMOS device, it is common to form grooves in source and drain regions and then epitaxially grow SiGe therein, which applies compressive stress to press a channel region, so as to improve the performances of the PMOS device. Likewise, for an NMOS device, it is becoming popular to epitaxially grow Si:C in source and drain regions, to achieve the same object. Specifically, various stress applying techniques, such as STI (Shallow Trench Isolation), SPT (Stress Proximity Technique), SiGe embedded source and drain, stressed metallic gate, and Contact Etching Stop Layer (CESL), have been proposed. Further, in small sized devices, it is common to adopt the LDD and Halo processes to suppress hot carrier effects and punch-through between the source and the drain. The LDD and Halo are generally achieved by means of ion implantation followed by annealing.
However, the ion implantation and annealing adopted in the conventional LDD and Halo processes may cause some problems. If the ion implantation is performed before the epitaxy in the source and drain regions, the implantation may cause crystal structures at surfaces of the source and drain grooves damaged, which has negative impacts on the following epitaxy in the source and drain regions. Otherwise, if the implantation is performed after the epitaxy in the source and drain regions, the implantation may cause the stress of the epitaxial layer released, resulting in reduced stress applied by the source and drain regions and thus degraded suppression of the SCE (Short Channel Effects) and DIBL (Drain Induced Barrier Lowering) effects. Further, a high temperature adopted in the annealing process may crystallize an amorphous layer formed by a pre-amorphization process. Furthermore, there is still a possibility that the TED (Transient Enhanced Diffusion) effect occurs and that doped elements cannot achieve a relatively high activation state.
In view of the above, there is a need for a novel transistor and a method of manufacturing the same, so as to more effectively guarantee the performances of the transistor.